Dumitru Potop-Butucaru

Junior Researcher (CR1), AOSTE team, INRIA Rocquencourt, France


Contact Information

dumitru.potop@inria.fr
http://www.DumitruPotop.net/
Tel: +33-139.63.55.80
Fax: +33-139.63.51.93
INRIA Rocquencourt
Domaine de Voluceau, BP 105
78153 Le Chesnay Cedex
France

Recent publications

D. Potop-Butucaru, R. de Simone, Y. Sorel, and J.-P. Talpin: Clock-driven distributed real-time implementation of endochronous synchronous specifications. In Proceedings EMSOFT'09 (PDF).
D. Potop-Butucaru, R. de Simone, Y. Sorel, and J.-P. Talpin: From Concurrent Multiclock Programs to Deterministic Asynchronous Implementations. In Proceedings ACSD'09 (PDF).
D. Potop-Butucaru, Y. Sorel: Optimized static real-time scheduling of communications on a broadcast bus. INRIA Research report RR-6655 (PDF).
D. Potop-Butucaru, R. de Simone, Y. Sorel: Deterministic execution of synchronous programs in an asynchronous environment. A compositional necessary and sufficient condition. INRIA Research report RR-6656 (PDF).

Compiling Esterel
by D. Potop-Butucaru, S. Edwards, and G. Berry
Springer, May 2007. ISBN: 0387706267

Book description at Esterel Technologies
Buy it from: Amazon , Barnes and Noble
D. Potop-Butucaru, R. de Simone, Y. Sorel: Necessary and sufficient conditions for deterministic desynchronization. To appear in Proceedings EMSOFT'O7 (PDF).
D. Potop-Butucaru, R. de Simone, Y. Sorel: From multi-clock constraints to multi-rate GALS executives. INRIA Research Report RR-6021, 2006 (PDF).
D. Potop-Butucaru, B. Caillaud: Correct-by-construction asynchronous implementation of modular synchronous specifications. In Fundamenta Informaticae, IOS Press, 2006. (PDF)
D. Potop-Butucaru, B. Caillaud, A. Benveniste: Concurrency in synchronous systems. In Formal Methods in System Design, 2006. (PDF)
D. Potop-Butucaru, R. De Simone, J.-P. Talpin: The synchronous hypothesis and synchronous languages. In R. Zurawski, ed., The Embedded Systems Handbook, CRC Press, 2005. (PDF)
D. Potop-Butucaru, R. De Simone: Optimizations for Faster Execution of Esterel Programs. In R. Gupta, P. LeGuernic, S. Shukla, and J.-P. Talpin, eds., Formal Methods and Models for System Design. Kluwer, 2004. (PDF)
Full list of publications. Other stuff (presentations, thesis).


Research

Current work: Computer-aided development of complex embedded systems and and systems-on-a-chip (SoC).
Relations between logical time and physical time for efficient real-time implementation of synchronous specifications. Emphasis on notions like periodicity, operation duration, causality, synchrony (main axis of work).
Asynchronous (GALS) implementation of synchronous specifications (with B. Caillaud and J.-P. Talpin ).
Efficient analysis and code generation for synchronous languages. Intermediate representation for analysis and compilation (with R. de Simone).
Joint use of control-flow and data-flow languages (Esterel, Signal) for system specification and efficient code generation.
More generally: Embedded system synthesis, Circuit synthesis, Formal methods, Efficient algorithms and data structures.
Software: I have developed the optimizing Esterel compiler grc2c (the best yet in terms of generated code speed) and the circuit optimizer scsimplify. Both were adapted for use in the commercial EsterelStudio suite. For more info, take the link below.
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Background

2005-now - Junior Researcher (CR2), AOSTE team, INRIA Rocquencourt, France.
2005 (feb-aug) - Post-doctoral fellow at Verimag, Grenoble, France. Funded by the ASSERT european projects.
2003-2004 - Post-doctoral fellow at IRISA Rennes, France. Member of the S4 project. Funded by the ARTIST and COLUMBUS european projects.
1999-2002 - Ph.D. of the Ecole des Mines de Paris (november 2002).
1998-1999 - Erasmus master student at Universite Pierre et Marie Curie, Paris, France.
1997-1998 - Teaching assistant at the Computer Science Department of the University of Bucharest, Romania.
1997-1999 - M.Sc. of the University of Bucharest, Romania.
1993-1997 B.Sc. of the University of Bucharest, Romania
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